The present invention relates to electronic cameras having high pixel density image pick-up devices and, more particularly, to electronic cameras which can provide smooth moving images to a liquid crystal display for recorded image confirmation with contracted evaluation value computing circuit for AE (automatic exposure), AF (auto focus) and AWB (auto white balance).
Electronic cameras generally called digital cameras or cam coders have an AE, an AF and an AWB function. For intelligently carrying out the processes of executing these functions, a method of control, in which evaluation values are obtained by dividing the image area into a plurality of divisions, is well known in the art. An exemplified construction of the electronic camera, in which the AE, AF and AWB are controlled by dividing the image area into a plurality of division areas, will now be described with reference to the block diagram shown in FIG. 1. An image is focused through a lens system 1 including a focus adjusting lens and an iris 2 for light dose adjustment on a CCD image pick-up device 3. The CCD image pick-up device 3 photoelectrically converts the focused image into an electric signal. A photographing circuit 4 processes the electric signal to generate an image signal. An A/D converter 5 converts the image signal to a digital signal.
When a CPU 17 detects that a recording mode has been set up by a mode setting switch 18, it controls the entire camera for operation in the recording mode. The digital signal from the A/D converter 5 is tentatively accumulated in a buffer 6, and then converted in a D/A converter to an analog signal, which is provided to a liquid crystal display (LCD) 9. The user can utilize the liquid crystal display as a view finder for setting the image to be picked up by watching the image displayed on the liquid crystal display 9. A compressor/decompressor 8 compresses the digital signal accumulated in the buffer 6 for recording the compressed digital signal as image data in a recording memory 10. When the CPU 17 detects that a play mode has been set up by the mode setting switch 18, it controls the entire camera for operation in the play mode. In this camera, the compressor/decompressor 8 decompresses the image data stored in the recording memory 10, and the expanded image data is tentatively accumulated in the buffer 6. The D/A converter 7 then converts the accumulated digital data to analog data, which is provided to the liquid crystal display 9. The user thus can confirm the recorded image by watching the image displayed on the liquid crystal display 9. The digital image signal from the A/D converter 5 is also provided to an AE, an AF and an AWB data detector 11, 12 and 13, respectively. The AE data detector 11 extracts a low frequency component of the image signal. A 1-st area integrator 14a integrates the extracted low frequency component for each of a plurality of divisions of the image area by using either an evaluation value memory 15a or 15b. Each integration value is preserved directly as AE evaluation value in the evaluation value memory 15a and 15b. 
Now, area integration executed by accessing the two evaluation value memories 15a and 15b will now be described with reference to the timing chart shown in FIG. 2. Data A which is obtained by exposure in a 1-st VD (vertical sync signal) period, is integrated in a 2-nd VD cycle in the 1-st area integrator 14a. When the 1-st area integrator 14a makes the memory accessing, it always makes memory accessing, and exclusively uses one evaluation value memory. Meanwhile, the CPU 17 seeks to read the result of area integration result of data A (i.e., evaluation result Axe2x80x2) from the evaluation value memory in a certain part of a 3-rd VD cycle. In this period, however, the 1-st area integrator 14a also seeks to make area integration of data B obtained by exposure in the 2-nd VD cycle by using the evaluation value memory. This means that it is inconvenient if only a single evaluation value memory is provided. Where two evaluation value memories are provided, one of them can be used for the area integration, while using the other for reading out the result of area integration (i.e., evaluation value). By alternately using these two evaluation value memories, it is possible to obtain the evaluation value for each VD (frame) period. For this reason, two evaluation value memories are provided for each of the 1-st to 3-rd area integrators 14a to 14c. 
Referring to the timing chart of FIG. 2, in the 2-nd VD cycle the 1-st area integrator 14a executes area integration of data A by using the evaluation value memory 15a, in the 3-rd VD cycle the CPU 17 reads out the result of area integration of data A, i.e., evaluation value Axe2x80x2, from the evaluation value memory 15a while the 1-st area integrator 14a makes area integration of data B by using the evaluation value memory 15b, and in the 4-th VD cycle the CPU 17 reads out evaluation value Bxe2x80x2 of data B from the evaluation value memory 15b while the 1-st area integrator 14a executes area integration of data C by using the evaluation data memory 15a. 
Referring back to the block diagram of FIG. 1, the AFD data detector 12 extracts a high frequency component of the image signal. A 2-nd area integrator 14b integrates the extracted high frequency component for each of the plurality of image area divisions by using either an evaluation value memory 15c or 15d. The result of the area integration is directly stored as AF evaluation value in either of the evaluation value memories 15c or 15d. The AWB data detector 13 separates color components (for instance R, G and B components) from the image signal. A 3-rd area integrator 14c integrates each separated color signal for each of the plurality of image area divisions by using either an evaluation value memory 15e or 15f. The result of the area integration is directly stored as AWB evaluation value in either of the evaluation value memories 15e and 15e. The CPU 17 can obtain the AE, AF and AWB values through the multiplexer 16. Since it is possible time-wise to read the three, i.e., AE, AF and AWB, evaluation values in one VD cycle, the CPU 17 can take out a desired evaluation value at a desired timing. Of curse, the CPU 17 can take the three evaluation values for each VD frame.
The CPU 17 controls the gain of the image signal from the image pick-up circuit 4 according to the AF evaluation value. Also, the CPU 17 controls the shutter speed of a device shutter in a CCD driver 19. (By the term xe2x80x9cdevice shutterxe2x80x9d is meant what can provide an equivalent effect to opening and closing a mechanical shutter by varying the photoelectric charge storage time of the image pick-up device.) The CPU 17 further drives the iris 2, which is coupled to a motor 22, via a motor driver 20 for exposure setting. The CPU 17 further drives a focusing lens, which is coupled to a motor 23, via a motor driver 2 according to the AF evaluation value. The CPU 17 further controls the gain of the image signal from the image pick-up device 4 for each color according to the AWB evaluation value, for white balance setting.
As shown above, the electronic camera having the construction as shown in FIG. 1, can execute intelligent AE, AF and AWF processes. On the demerit side, however, the camera requires three area integrators and six memories therefor, thus leading to an extremely large circuit scale. FIG. 3 shows a different example of the electronic camera construction, which uses a common area integrator and common evaluation value memories for decreasing circuit scale. A different part of the electronic camera shown in FIG. 3 from the one shown in FIG. 1 will be described. The outputs of the AE, AF and AWF data detectors 11, 12 and 13 are selectively coupled by a switch 24 to a single area integrator 14. Actually, since the AE, AF and AWF evaluation values are detected from the image signal, the CPU 17 controls the switching of the switch 24 in synchronism to the VD signal from the image pick-up circuit 4 for sequentially connecting the AE, AF and AWB data detectors 11-13 to the area integrator 14.
The area integrator 14 makes area integration via the multiplexer 16 by using either a first or a second evaluation value memory 15-1 or 15-2. The CPU 17 accesses the memory, which is not used for the area integration, via the multiplexer 16 to sequentially obtain the AE, AF and AWB evaluation values in synchronism to the VD signal. The CPU 17 then executes the AE, AF and AWF processes sequentially with the obtained evaluation values in synchronism to the VD signal. In the case of the electronic camera shown in FIG. 3, the AE, AF and AWF evaluation values can be taken only once in 3 VD cycles. With usual electronic cameras and column decoders, however, the VD (frame) rate is 60 Hz, so that their output movie images have no abnormal sense.
In the mean time, recently, the pixel density increase of digital cameras is in rapid progress. High pixel density images require long processing time because of great amount of their data. Long processing time inevitably results in low frame rate. In the electronic camera shown in FIG. 3, which is intended to reduce the circuit scale for cost reduction, and in which the AE, AF and AWB processes are executed only once in 3 VD cycles, if the frame rate is reduced, the interval of the individual processes is increased, resulting in output movie images which are very uncomfortable to watch. For example, such problems may arise that in the AE control the instant of brightness switching is clearly known, and that in the AF control the xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d times of the focusing lens are clearly discriminated from each other.
The present invention has been made in order to solve the above problems inherent in the prior art electronic cameras, and its specific object is to provide an electronic camera, which uses an image pick-up device of a very high pixel density although it is impossible to obtain the three, i.e., AE, AF and AWB, evaluation values for every frame due to a reduced scale of the circuit for the evaluation value computation, and can provide smooth movie images not giving any sense of uncomfortability and giving rise to no trouble in the photography in spite of a reduced movie image frame rate.
Other objects of the present invention are as follows.
A first object of the invention is to provide an electronic camera, which permits continuous images not giving any sense of uncomfortability to be obtained without possibility of sudden output change even in its application to an electronic camera, in which the frame switching time is long as in the case of using an image pick-up device of a high pixel density.
A second object of the invention is to provide an electronic camera, which can suppress image brightness variations even in the case when photoelectric charge is accumulated in a cycle capable of flicker cancellation.
A third object of the invention is to provide an electronic camera, which permits movie image output free from brightness hunting and giving no sense of uncomfortability in smoothness to be obtained even in the case when the timings of setting the photoelectric charge accumulation time and setting the gain control are deviated from each other.
A fourth object of the invention is to provide an electric camera, which permits smooth movie images to be obtained even at the time of auto focus control.
A fifth object of the invention is to provide an electronic camera, which can smoothly cope with brightness changes even when the scene is changed during movie image display.
A sixth object of the invention is to provide an electronic camera, which is free from delay generation even in a control signal process requiring a considerably long process time.
A seventh object of the invention is to provide an electronic camera, an electronic camera, which permits highly accurate auto focus control or auto focus control.
An eighth object of the invention is to provide an electronic camera, which is free from flicker generation even when it uses an image pick-up device of high pixel density.
A ninth object of the invention is to provide an electronic camera, which features smooth movie image area motion and is less subject to AWB or AE variations.
According to a first aspect of the present invention, there is provided an electronic camera comprising an image pick-up device, means for setting the photoelectric charge accumulation time of the image pick-up device, an image pick-up circuit for including gain control means, for processing a signal read out from the image pick-up device to obtain an image signal, and control signal processing means for sequentially obtaining a focus control signal, an exposure control signal and a white balance control signal for each image frame from the image signal from the image pick-up device and selectively controlling individual signal processes, wherein the gain of the image signal and the photoelectric charge accumulation time are controlled for each image frame by using the control signals from the control signal processing means.
With this construction, the image signal gain and the photoelectric charge accumulation time are controlled by using the control signals for each frame even in an electronic camera, in which the frame switching time is considerably long as in the case of using an image pick-up device of high pixel density. Thus, the gain control and the photoelectric charge accumulation time control are not suddenly changed, and it is possible to obtain continuous images not giving any sense of uncomfortability even when the images are displayed on a monitor or the like.
According to a second aspect of the present invention, there is provided the electronic camera according to first aspect, wherein the means for setting the photoelectric charge accumulation time of the image pick-up device can set the photoelectric charge accumulation time discretely so that the photoelectric charge accumulation time can be changed to values free from flicker, and sets the photoelectric charge accumulation time variably in combination with gain control by gain control means.
In an area where the fluorescent lamp is driven at 100 Hz, when photoelectric charge is accumulated in a time which is inversely proportional to an integral multiple of 50 Hz in order eliminate flicker on a monitor screen or the like, the photoelectric charge accumulation amount is changed greatly whenever the photoelectric charge accumulation time is changed, thus greatly changing the image brightness. By combining the photoelectric charge accumulation time changes with the gain control as in the above construction, it is possible to reduce image brightness variations and obtain smooth images not giving any sense of uncomfortability.
According to a third aspect of the present invention, there is provided the electronic image pick-up means according to the first aspect, wherein the means for setting the photoelectric charge accumulation time of the image pick-up device sets the level of the image signal with combination of the setting of the photoelectric charge accumulation time and gain control by gain control means, and the gain of image signal based on photoelectric charge accumulated after control of the photoelectric charge accumulation time of the image pick-up device is controlled after one vertical sync cycle.
Deviation of the timings of the photoelectric charge accumulation time setting and the gain control setting may result in failure of smooth brightness increase or reduction, giving rise to hunting. By using the above construction, it is possible to improve the exposure control accuracy and obtain smooth moving images not giving any sense of uncomfortability.
According to a fourth aspect of the present invention, there is provided the electronic camera according to one of the first to third aspects, which further comprises photographing lens focus driving means driven for every frame.
This kind of photographing lens driving for every frame may improve the intermittent movement of the photographing lens and obtain smooth moving images.
According to a fifth aspect of the present invention, there is provided the electronic camera according to one of the first to fourth aspects, wherein gain control by gain control means and control of the photoelectric charge accumulation time of the image pick-up device are controlled by increasing or reducing them in predetermined ratios.
By this structure, it is possible to smoothly cope with the brightness change due to scene change.
According to a sixth aspect of the present invention, there is provided the electronic camera according to one of the first to fifth aspects, wherein the control signal processing means makes preparations for a signal process on a control signal to be provided by signal processing one vertical sync cycle afterwards while executing a signal process on a pertinent one of the control signals.
With this construction, it is possible to execute without time delay the control signal processing which requires a large amount of computations and complex processings.
According to a seventh aspect of the present invention, there is provided the electronic camera according to one of the first to sixth aspects, wherein the control signal processing means first executes the signal process on the exposure control signal and then executes the signal processes on the focus control signal and the white balance control signal.
By using this auto focus control and white balance control with the exposure condition set based on the automatic exposure control, it is possible to adjust appropriate or optimum exposure extent necessary for the control and obtain the auto focus control and white balance control with high accuracy.
According to an eighth aspect of the present invention, there is provided the electronic camera according to one of the first to seventh aspects, wherein the means for setting the photoelectric charge accumulation time of the image pick-up device sets the time of switching of the photoelectric charge accumulation time for each frame to an integral multiple of 1/100.
Thus it is possible to suppress the flicker even with the image device having high pixel density.
According to a ninth aspect of the present invention, there is provided the electronic camera according to the fourth aspect, wherein the summation of the time necessary for the driving of the photographing lens by the photographing lens focus driving means and the computation time of the signal process on the focus control signal from the control signal processing means does not exceed one vertical sync cycle time.
With this construction, the movement of moving images may be smoothed and the changes in AWB and AE may be reduced.
Other objects and features will be clarified from the following description with reference to attached drawings.